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order from logic marketing document br1458s/d semiconductor technical data ? motorola, inc. 1994 9/94 rev 0 motorola reliability report for the lcx product family introduction/statement of purpose motorola reliability and quality assurance motorola has a long standing reputation for manufacturing products of excellent quality and reliability since the introduction of the first car radio in 1928. this has helped motorola to become one of the largest corporations exclusively devoted to electronics. in today' s semiconductor marketplace, two important elements for the success of a company are its quality and reliability systems. they are interrelated, reliability being quality extended over the expected life of a product. for any manufacturer to remain in business, its products must meet or exceed basic quality and reliability standards and customer needs. at motorola, the most stringent and demanding definitions of quality and reliability are used. quality ? reduction of variability around a target so that conformance to customer requirements and expectations can be achieved in a costef fective way ? the probability that a device (equipment, parts) will have performance characteristics within specified limits ? fitness for use reliability ? quality in time and environment ? the probability that our semiconductor devices, which initially have satisfactory performance, will continue to perform their intended function for a given time in usage environments at motorola, our reliability and quality assurance program is designed to generate ongoing data for both reliability and quality for the various product families. both reliability and quality monitors are performed on the dif ferent major categories of semiconductor products. these monitors are designed to test the product' s design and material as well as to identify and eliminate potential failure mechanisms to ensure reliable device performance in a areal worldo application. thus, the primary purpose of the program is to identify trends from generated data, so if need be, corrective action(s) can be taken toward improving performance. in addition, this reliability and quality data can be utilized by our customers for failure rate predictions. it is the explicit purpose of this communication to inform the customer of our lcx qualification results. in addition, we have provided a general definition of our reliability and quality assurance program.
2 motorola
3 motorola table of contents device description e mc74lcx244 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . processing information 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . processing summary 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . qualification introduction 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . intrinsic reliability 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . electromigration 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . hot carrier injection (hci) 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dielectric integrity 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . extrinsic reliability 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . high temperature bias (htb) 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . temperature cycling 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal shock 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . temperature humidity bias (thb) 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . pressure temperature humidity (pth) 5 . . . . . . . . . . . . . . . . . . . . . . . surface mount preconditioning 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . physical dimensions 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . solderability 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . marking permanency 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . process qualification information 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . process qualification summary 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . intrinsic reliability results 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . extrinsic reliability results 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package qualification information 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package qualification summary 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package qualification results 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . thermal management considerations 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . reliability audit program summary 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 motorola lcx device description the lcx logic family , the first low voltage cmos family with 5v tolerant inputs and outputs, is manufactured on the h4c apluso 75% cmos (double layer metal) process at mos 6. the lcx family emphasizes low power , low switching noise, and fast switching speeds. it will be assembled in the qualified 20 ld. soic package and 20 ld. tssop package. the h4c apluso 75% cmos process in mos 6 was qualified using the lcx logic family's e76s maskset. lcx processing information processing summary e h4c aplus,o 75% cmos (double layer metal) general process type cmos on epi effective channel length min. target=0.65 m m process complexity single poly, double metal gate processing gate oxide thickness 150? gate terminal phosphorous doped polysilicon (pocl) n+ source drain dopant phosphorous & arsenic p+ source drain dopant boron (bf2) metallization processing metal composition alsicu w/tin barrier (m1) alsicu (m2) passivation processing passivation type double layer, nitride over psg oxide electrical characteristics field threshold voltage >12v punchthrough voltage >12v gate oxide breakdown >14v
5 motorola lcx qualification introduction lcx qualification consisted of intrinsic and extrinsic reliability testing. intrinsic reliability concerns device degradation issues and is assessed via electromigration, hot carrier injection and dielectric breakdown measures. extrinsic r eliabilit y a ddresse s b ot h p rocessin g a nd packaging related issues and utilizes several tests: high temperature b ias , t emperatur e c ycling, p ressure temperature h umidit y, t herma l s hock, t emperature humidity bias, surface mount preconditioning, physical dimensions, s olderability a n d m arkin g p ermanency. (included below are definitions of the aforementioned terms.) intrinsic reliability electromigration electromigration is the movement of metal in the direction of electron flow. this is accelerated by high current densities and temperatures which result in metal void and/or collection (hillock) formations, and ultimately shorts. design rules specify m inimu m m eta l w idth s a n d m aximu m c urrent densities to circumvent electromigration issues. hot carrier injection (hci) hot carrier injection is the result of electron scattering and subsequent trapping in the gate oxide of mos devices. scattering is a function of electron velocity and thus electric fields a n d t emperature . u ltimately , c arrie r m obilit y a nd transconductance are reduced causing threshold voltage shifts. processing conditions are set to minimize hot carrier generation rates and gate trapping ef ficiencies. dielectric breakdown dielectric b reakdow n r esult s i n t h e f ormatio n o f a conductive path connecting onceisolated conducting layers. high v oltag e i nduce d c harg e i njectio n a n d t rapping accelerates this breakdown. dielectric integrity is maximized via uniform depositional thickness, and dielectric quality is achieved through minimizing impurity , charge, and defect levels. extrinsic reliability high temperature bias (htb) high temperature bias (htb) testing is performed to accelerate failure mechanisms which are activated through the application of elevated temperatures and the use of biased operating conditions. the temperature and voltage conditions used in the stress are dependent on the product under stress. however , the typical ambient temperature is 145 c with the static bias applied equal to or greater than the data sheet nominal value. temperature cycling (milstd833d1010c) temperature cycle testing accelerates the ef fects of thermal e xpansio n m ismatc h a mon g t h e d ifferent components within a specific die and packaging system. this test is typically performed per milstd883d method 1010c with the minimum and maximum temperatures being 65 c and +150 c, respectively . during temperature cycle testing, devices are inserted into a cycling system and held at the cold dwell temperature for at least ten minutes. following this cold dwell, the devices are heated to the hot dwell where they remain for another ten minute minimum time period. the system employs a circulating air environment to assure rapid stabilization at the specified temperature. the dwell at each extreme, plus the two transition times of five minutes each (one up to the hot dwell temperature, another down to the cold dwell temperature), constitute one cycle. thermal shock (milstd833d1010c) the objective of thermal shock testing is the same as that for t emperatur e c ycl e t esting , t ha t i s , t o e mphasize differences in expansion coef ficients for components of the packaging s ystem . h owever, t herma l s hoc k p rovides additional stress, in that the device is exposed to a sudden change in temperature due to a maximum transfer time of ten seconds, as well as the increased thermal conductivity of a liquid a mbient . t hi s t es t i s t ypicall y p erforme d p er milstd883d method 101 1c with minimum and maximum temperatures being 65 c to +150 c, respectively. devices are placed in a bath and cooled to minimum specified temperature. after being held in the cold chamber for five minutes minimum, the devices are transferred to an adjacent chamber at the maximum specified temperature for an equivalent time. t wo five minute dwells plus two ten second transitions constitute one cycle. temperature humidity bias (thb motorola std) this stress is performed to accelerate the ef fects of moisture p enetration , w it h t h e d ominan t e ffect b eing corrosion. c ondition s e mploye d d urin g t his t es t a r e a temperature of 85 c, humidity of 85% rh, and a nominal bias level. pressure temperature humidity (pth motorola std) this stress is performed to accelerate the ef fects of moisture p enetration , w it h t h e d ominan t e ffect b eing corrosion. this test detects similar failure mechanisms as thb but at a greatly accelerated rate. conditions employed during this test are a temperature of 121 c, pressure of 15psig or greater , humidity of 100% rh, unbiased. surface mount preconditioning (motorola std) preconditioning t est s a r e p erformed t o s imulat e t he customer board mount process where surface mount parts are subjected to a high temperature for a short duration. these tests detect mold compound delamination from the die and leadframe which can result in reliability failures. the dominant f ailure m echanis m i s c orrosion , b u t o ther
6 motorola stressrelated problems could also occur like fractured wirebonds, passivation cracks, smeared metal on die, etc. the conditions typically used are 245 c for ir reflow and 260 c for solder immersion. for small pitch packages, a 260 c oil immersion is substituted for the 260 c solder to avoid solder bridging of the leads. physical dimensions (milstd883d2016) the purpose of this test is to verify the external dimensions of the device are in accordance with the case outline specification. this test is typically performed per milstd 883d method 2016. solderability (milstd883d2003) the purpose of this test is to determine the solderability of all terminations which are normally joined by a soldering operation. this test is typically performed per milstd 883d method 2003. the test verifies the ability of these terminations to be wetted or coated by solder , and to predict suitable fillet when dip soldered. an accelerated aging test is included in this method which simulates a minimum of six months natural aging under a combination of various storage conditions that have a deleterious ef fect on the solderability . marking permanency (motorola std) the purpose of this test is to verify the device markings will not become illegible when subjected to solvents, and the solvents will not cause any mechanical, electrical, damage or deterioration, of the materials or finishes. this test is typically performed per motorola standard.
7 motorola process qualification information process qualification summary the h4c apluso 75% cmos (double layer metal) process q ualificatio n c onsisted o f i ntrinsi c r eliability testing ( electromigration , h o t c arrie r i njection , a nd dielectric breakdown) and extrinsic reliability testing (hig h t emperatur e b ias , t emperatur e c ycling , a nd pressure t emperature humidity), the results of which follow. intrinsic reliability ? electromigration no significant degradation . . . . . . . . ? hci no significant degradation . . . . . . . . . . . . . . . . . . . ? dielectric breakdown no significant degradation . . . . extrinsic reliability ? htb zero failures . . . . . . . . . . . . . . . . . . ? temperature cycling zero failures . . . . ? pth zero failures . . . . . . . . . . . . . . . . . . intrinsic reliability results device qualification electromigration electromigration evaluation of mos 6 metals used in the h4c o plus o 7 5 % c mo s ( doubl e l aye r m etal) p rocess revealed an acceptable metallization process for a minimum lifetime of 10 years at 100 c with < .01% cumulative failures. hot carrier injection hot carrier injection testing resulted in less than a 10% change i n t ransconductanc e o ve r t h e l ifetim e o f t he transistor. worst case hci occurs at cold temperature, so low temperature bias was performed at 10 c as shown below. zero process related rejects occurred after 504 hours of oplife at 10 c. low temperature bias (10 c, 3.6v bias) lot # sample size 40 hours 250 hours 504 hours s37201.4 72 0 rejects 0 rejects 0 rejects dielectric breakdown the current conduction and qbd data taken in mos 6 was used to calculate an intrinsic gate oxide lifetime of 1364 years. this estimated lifetime greatly exceeds the expected lifetime of the device. extrinsic reliability results/data process qualification the reliability testing consisted of high t emperature bias (145 c, 3.6v bias), t emperature cycling (65 c to 150 c), and pth (121 c, 15psig, & 100% rh). samples from three wafer lots; s37201.4, s41657.2, and s37744.1 were tested as specified above. w afer lot # s37201.4 was a nominal lot. wafer lot # s41657.2 was a metal and dielectric split lot. the metal and dielectric layers were run at the maximum and minimum thickness specifications in order to account for worst and best case step coverage. wafer lot # s37744.1 was a vt and lef f split lot. the vt and leff were run at minimum and maximum specifications in order to account for worst and best case leakage, worst and best case speeds, and worst case translation window . zero process related rejects occurred after 504 hours of oplife, 600 temp cycles, and 240 hours of pth. high temperature bias (145 c, 3.6v bias) lot # sample size 40 hours 250 hours 504 hours s37201.4 84 0 rejects 0 rejects 0 rejects s41657.2 304 0 rejects 0 rejects 0 rejects s37744.1 225 0 rejects 0 rejects 0 rejects fit = 14.5; stress temp = 145 c; equiv temp = 55 c; activation energy = 0.7ev ; confidence level = 60%; device hours = 308,952. temperature cycle (65 c to 150 c) lot # sample size 100 cycles 600 cycles s37201.4 76 0 rejects 0 rejects s41657.2 286 0 rejects 0 rejects s37744.1 227 0 rejects 0 rejects pressure temperature humidity (121 c, 15 psig, 100% rh) lot # sample size 96 hours 240 hours s37201.4 43 0 rejects 0 rejects s41657.2 168 0 rejects 0 rejects s37744.1 223 0 rejects 0 rejects the h4c apluso 75% cmos (double layer metal) process in mos 6 has been qualified and approved based on the results of the above intrinsic and extrinsic reliability results.
8 motorola package qualification mc74lcx244 is being of fered in both 16ld soic and 20ld tssop packaging. both are currently qualified packages. as the t sso p p ackage i s a n ewe r t echnology , r elevant qualification data has been included in this report. all reliability t est s h av e p asse d s uccessfully , i ncluding preconditioning tests used to simulate customer board mount processes (see below). furthermore, based on reliability results, drypack is not required for this package type. included below is general information concerning the tssop package and results relating to the aizu tssop qualification. package qualification summary tssop leads op life temperature cycle thermal shock thb surface mount preconditioning solderability marking permanency physical dimension 14 pass pass pass pass pass pass pass pass 16 pass pass pass pass pass pass pass pass 20 pass pass pass pass pass pass pass pass summary package information ? package material hitachi cel 9200n ? leadframe material copper ? plating 80/20 tin/lead solder plate ? die attach epoxy sumitomo crm 1033b ? wire bond material 1.0 mil gold ? wire bond method thermosonic ball ? theta ja (20 ld tssop) 140 deg c/w ? 14/16lead flag size 83 x 93 mils ? 20lead flag size 83 x 120 and 1 10 x 120 mils the aizu package dimensions are as follows: package width length pitch total mounting height 14/16-lead 4.4mm 5.0mm 6.5mm 1.1mm 20-lead 4.4mm 6.5mm 6.5mm 1.1mm qualification data is based on devices from the metal gate, high speed, and fact families with various die sizes as listed below: lot # lead count device die size 1 14 mc14066b 64 x 64 mils 2 14 mc74act08 41 x 45 3 16 mc74hc76 72 x 83 4 16 mc74hc175 68 x 73 5 16 mc74act163 63 x 50 6 20 mc74hc244a 74 x 74 7 20 mc74ac245 69 x 81 8 20 mc74act534 68 x 67 9 20 mc74hct245a 82 x 104
9 motorola package qualification results htb t a = 125 c, nominal bias lot # leads 168 hours 504 hours 1000 hours 1 14 ld 0/45 0/45 0/45 6 20 ld 0/45 0/45 0/45 7 20 ld 0/45 0/45 0/45 temperature cycle (milstd883, method 1010c) 65 to +150 c lot # leads 600 hours 1000 hours 1 14 ld 0/45 0/45 2 14 ld 0/76 0/76 3 16 ld 0/45 0/45 4 16 ld 0/45 0/45 5 16 ld 0/74 0/74 6 20 ld 0/45 0/45 7 20 ld 0/45 0/45 8 20 ld 0/73 0/73 9 20 ld 0/45 0/45 thermal shock (milstd883, method 1011c) 65 to +150 c lot # leads 300 cycles 500 cycles 1000 cycles 1 14 ld 0/22 0/22 0/22 3 16 ld 0/22 0/22 0/22 4 16 ld 0/22 0/22 0/22 6 20 ld 0/22 0/22 0/22 7 20 ld 0/22 0/22 0/22 thb e 85 c/85% r.h., nominal bias lot # leads 168 hours 504 hours 1000 hours 1 14 ld 0/45 0/45 0/45 3 16 ld 0/45 0/45 0/45 4 16 ld 0/45 0/45 0/45 6 20 ld 0/45 0/45 0/45 7 20 ld 0/45 0/45 0/45 preconditioning tests: ir reflow preconditioning is performed to simulate the customer board mount process where surface mount parts are subjected to ir temperatures of 245 c max. all preconditioned lots received 30x external visual for package cracks. no cracks were present for any of the preconditioned lots. ir reflow preconditioning e 24 hrs 85/85 + 2 cycles ir reflow at 240 c + pth (121 c, 100%rh, 15psig) lot # leads 96 hours 192 hours 288 hours 1 14 ld 0/45 0/45 0/45 3 16 ld 0/45 0/45 0/45 4 16 ld 0/45 0/45 0/45 6 20 ld 0/45 0/45 0/45 7 20 ld 0/45 0/45 0/45 9 20 ld 0/45 0/45 0/45 ir reflow preconditioning e 168 hrs 85/85 + 3 cycles ir reflow at 245 c + pth (121 c, 100%rh, 15psig) lot # leads 96 hours 2 14 ld 0/41 5 16 ld 0/40 8 20 ld 0/41 9 20 ld 0/45 ir reflow preconditioning e 168 hrs 85/85 + 3 cycles ir reflow at 245 c + t emp cycle (65 to +150 c) lot # leads 100 cycles 600 cycles 1000 cycles 2 14 ld 0/71 0/71 0/71 5 16 ld 0/73 0/73 0/73 8 20 ld 0/72 0/72 0/72 9 20 ld 0/76 0/76 0/76 solder immersion preconditioning: solder immersion is performed to simulate the customer backside board assembly process where surface mount parts are subjected to a 260 c wave solder . based on the following data, the 14/16/20 tssop can be backside board mounted. solder preconditioning e 168 hrs 85/85 + 10 second oil/solder immersion at 260 c + pth (121 c, 100%rh, 15psig) lot # leads 48 hours 96 hours 2 14 ld 0/20 0/20 5 16 ld 0/21 0/21 8 20 ld 0/25 0/25 9 20 ld 0/45 0/45 solder preconditioning e 168 hrs 85/85 + 10 second oil/ solder immersion at 260 c + t emp cycle (65 to +150 c) lot # leads 100 cycles 600 cycles 1000 cycles 2 14 ld 0/16 0/16 0/16 5 16 ld 0/21 0/21 0/21 8 20 ld 0/22 0/22 0/22 9 20 ld 0/76 0/76 e
10 motorola solderability (motorola standard) lot # leads 8 hour steam age results 2 hour bake at 175 c results 2 14 ld 0/3 0/3 5 16 ld 0/3 0/3 8 20 ld 0/3 0/3 marking legibility (motorola standard) lot # leads results 2 14 ld 0/11 5 16 ld 0/11 8 20 ld 0/11 physical dimensions (case outline) lot # leads results 2 14 ld 0/3 5 16 ld 0/3 8 20 ld 0/3 terminal strength (motorola standard) a. tensile pullout strength e 100g, 10 sec. lot # leads results 4 16 ld 0/11 b. bending test e 50g, 2 times lot # leads results 4 16 ld 0/11 salt water spray e t a = 35 c, 5% nacl solution, 24 hours lot # leads results 3 16 ld 0/11 6 20 ld 0/11 7 20 ld 0/11 xray for w ire sweep and internal v oids (motorola standard) lot # leads results 2 14 ld 0/5 3 16 ld 0/5 4 16 ld 0/5 5 16 ld 0/5 8 20 ld 0/5
11 motorola thermal considerations reliability of plastic packages although today' s plastic packages are as reliable as ceramic packages under most environmental conditions, as the junction temperature increases a failure mode unique to plastic packages becomes a significant factor in the long term reliability of the device. modern plastic package assembly utilizes gold wire bonded t o a luminu m b ondin g p ad s t hroughou t t he electronic s i ndustry. a s t h e t emperatur e o f t h e s ilicon (junction temperature) increases, an intermetallic compound forms between the gold and aluminum interface. this intermetallic formation results in a significant increase in the impedance of the wire bond and can lead to performance failure of the af fected pin. with this relationship between intermetallic formation and junction temperature established, it is incumbent on the designer to ensure that the junction temperature for which a device will operate is consistent with the long term reliability goals of the system. reliability studies were performed at elevated ambient temperatures (125 c) from which an arrhenius equation (eq 1), relating junction temperature to bond failure, was established. the application of this equation yields the values in t able 1. this table relates the junction temperature of a device in a plastic package to the continuous operating time before 0.1% bond failure (1 failure per 1000 bonds). ( eq 1 ) t = 6.376 10 9 e 11554.267 273.15 + t j where: t = time to 0.1% bond failure table 1. tj vs time to 0.1% bond failure junction temp. ( c) time (hours) time (yrs.) 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.1 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 thermal management as i n a n y s ystem , p rope r t herma l m anagemen t i s essential to establish the appropriate trade-of f between performance, density , reliability and cost. in particular , the designer should be aware of the reliability implication of continuously o peratin g s emiconductor d evice s a t h igh junction temperatures. the increasing popularity of surface mount devices (smd) is putting a greater emphasis on the need for better thermal management of a system. this is due to the fact that smd packages generally require less board space than their through hole counterparts so that designs incorporating smd technologies have a higher thermal density . t o optimize the thermal management of a system it is imperative that the user understand all of the variables which contribute to the junction temperature of the device. the v ariables i nvolve d i n d eterminin g t h e j unction temperature of a device are both supplier and user defined. the supplier , through lead frame design, mold compounds, die size and die attach, can positively impact the thermal resistance and the junction temperature of a device. motorola continually experiments with new package designs and assembly techniques in an attempt to further enhance the thermal performance of its products. it can be argued that the user has the greatest control of the v ariables w hic h c ommonl y i mpac t t h e t hermal performance of a device. depending on the environment in which an ic is placed, the user could control over 75% of the current that flows through the device. ambient temperature, air flow and related cooling techniques are the obvious user controlled variables, however , pcb substrate material, layout density, size of the air-gap between the board and the package, amount of exposed copper interconnect, use of thermally-conductive epoxies and number of boards in a box and output loading can all have significant impacts on the thermal performance of a system. pcb substrates all have dif ferent thermal characteristics, these characteristics should be considered when exploring the pcb alternatives. the user should also account for the different power dissipations of the dif ferent devices in his system and space them on the pcb accordingly . in this way, the heat load is spread across a larger area and ahot spotso do not appear in the layout. copper interconnect traces act as heat radiators, therefore, significant thermal dissipation can be achieved through the addition of interconnect traces on the top layer of the board. finally , the use of thermally conductive epoxies can accelerate the transfer of heat from the device to the pcb where it can more easily be passed to the ambient. the advent of smd packaging and the industry push towards smaller, denser designs makes it incumbent on the designer to provide for the removal of thermal energy from the system. users should be aware that they control many of the variables which impact the junction temperatures and, thus, to some extent, the long term reliability of their designs. calculating junction temperature the following equation can be used to estimate the junction temperature of a device in a given environment: t j = t a + p d q ja where: t j = junction temperature t a = ambient temperature p d = power dissipation q ja = avg pkg thermal resistance (junction ambient)
12 motorola power dissipation equation p d v cc c p v cc s i 1 f out i v cc [ i cc n ] 1 2 (v cc v oh ) (v oh v ol ) s i 1 c l i f out i h i 1 v oh r d i 3 4 (v ol ) (v oh v ol ) s i 1 c l i f out i l i 1 (v cc v ol ) r u i 5 6 the power dissipation equation is made up of five major factors controlled by the user which contribute to increased power dissipation: 1. frequency of operation (output switching frequency) 2. input voltage levels 3. output loading (capacitive and resistive) 4. v cc level 5. duty cycle each of these five factors are addressed in the estimating equation except duty cycle. duty cycle can be addressed by aweightingo t h e p owe r d issipatio n e quation t erms appropriately. the first current term is i ccd , with the device unloaded. it is caused by the internal switching of the device. static i cc is so small for lcx, that when estimating power dissipation, it is ignored. c p v cc s i 1 f out i this term represents the i cc current with absolutely no load. this measurement is taken without the output pins connected to the board. the c p for a device is calculated by: c p i cc (@50mhz) i cc (@1mhz) v cc (49mhz)s aso is the number of outputs switching. c p may vary slightly from part to part within a product family . the next term is from current due to holding the cmos inputs at v cc 0.6v rather than at the rail voltages. this term becomes insignificant as load and frequency increase. d i cc n d i cc is the through current when holding the input high of a device to v cc 0.6v . this value is typically 300 m a or less. ano is the number of inputs held at this level. the third term is current through the upper structure of the device. it is caused by the external capacitive load and the output frequency . if a capacitive load exists then this term can become very significant. (v oh v ol ) s i 1 c l i f out i v oh v ol is the voltage swing of the output. c l is the output load (this could vary from output to output). f out is the output frequency which can also vary from output to output. the fourth term stems from current through the upper structure due to an external resistive load to ground. as the output frequency increases, the measured current approaches that of static high outputs. h i 1 v oh r d i r d is an external pulldown resistor . a dif ferent value load could be applied to each output. the f ift h c urren t t er m i s d etermine d b y t h e o utput capacitive load and the output frequency on the lower structure of the device. if this load exists than this term is also significant. (v oh v ol ) s i 1 c l i f out i all variables are the same as with the third term with the exception that this is current flowing through the lower structure of the ic. this current is not i cc , but rather current that is asinkedo from an external source. the final term is due to an external load connected to v cc . this term includes both switching and static low outputs. l i 1 (v cc v ol ) r u i as with term five, this is current that flows through the lower structure of the ic. this current too is not i cc .
13 motorola example of thermal calculations junction temperature can be estimated using the following equation: t j = ( q ja p d ) + t a where: t j = junction temperature ( c) q ja = thermal resistance (junctiontoambient) p d = power dissipation at a t j t a = ambient temperature ( c) example of lcx t j calculation 1. calculate current consumption: for example, the lcx244' s c p is 25pf . let v cc = 3v ; operating temperature = 85 c; f out = 50mhz; for 4 outputs switching; hold 2 inputs low and 2 inputs high (at v cc 0.6v); c l = 100pf; 500 w pulldown; no pullup. 25pf 3v 4 i 1 50mhz 0.3ma(2) 1 2 =15ma + 0.6ma = 15.6ma these unloaded terms contribute only 10% of the total i cc current. (2.8v 0.2v) 4 i 1 100pf(50mhz) 6 i 1 2.8v 500 3 4 = 52ma + 33.6ma = 85.6ma in this example, terms three and four contribute over 55% of the total i cc current. this part of i cc is entirely due to external loading. (2.8v 0.2v) 4 i 1 100pf(50mhz) 6 i 1 3v 0.2v 5 6 = 52ma + 0 = 52ma these terms are not i cc currents, but rather currents asinkedo by the lower structure of the device. the total current from all terms is 153.2ma. 2. finding pd (v x i) when calculating the total power dissipation of the device, the first two terms are multiplied by v cc , which in this example is 3v(15.6ma) = 46.8mw the third and fourth terms are multiplied by the voltage drop across the upper structure of the device, v cc v oh . this is approximately 0.2v . 0.2v(85.6ma) = 17.1mw the fifth and sixth terms are multiplied by the voltage drop across the lower structure of the device, v ol . 0.2v(52ma) = 10.4mw the total estimated power dissipation of an lcx 244 with 4 outputs switching, at 85 c, with v cc =3v, with 2 outputs held static low , and 2 inputs at 2.4v with 100pf capacitive loads, 500 w pulldowns, and 50mhz switching frequency is: 74.3 mw 3. q ja value the q ja for a 20pin tssop is approximately 140 c/w. 4. final calculations for t j for the lcx244 t j = (p d q ja ) + t a = (0.0743w 140 c/w) + 85 c = 95.4 c. lcx runs cool e well below the point for reliability worries. using the arrhenius equation (eq 1 on page 1 1), the time to 0.1% bond failures is approximately 30 years.
14 motorola system considerations the manner in which an ic package is mounted and positioned i n i t s s urroundin g e nvironmen t w il l h ave significant ef fects on operating junction temperatures. these conditions are under the control of the system designer and are worthy of serious consideration in pc board layout and system ventilation and airflow . forcedair cooling will significantly reduce q ja . air flow parallel to the long dimension of the package is generally a few percent more ef fective than air flow perpendicular to the long dimension of the package. in actual board layouts, other components c a n p rovid e a i r f lo w b lockin g a nd f low turbulence, which may reflect the net reduction of q ja of a specific component. external heat sinks applied to an ic package can improve thermal resistance by increasing heat flow to the ambient environment. heat sink performance will vary by size, material, design, and system air flow . heat sinks can provide a substantial improvement. package mounting can affect thermal resistance. surface mount p ackage s d issipat e s ignificant a mount s o f h eat through the leads. improving heat flow from package leads to ambient will decrease thermal resistance. ? metal (copper) traces on pc boards conduct heat away from the package and dissipate it to the ambient; thus the larger the trace area the lower the thermal resistance. ? package standoff has a small ef fect on q ja . boards with higher thermal conductivity (ceramic) may show the most pronounced benefit. ? the use of thermally conductive adhesive under so packages can lower thermal resistance by providing a direct heat flow path from the package to board. naturally high thermal conductivity board material and/or cool board temperatures amplify this effect. ? high thermal conductive board material will decrease thermal resistance. a change in board material from epoxy laminate to ceramic will help reduce thermal resistance. conclusion thermal m anagemen t r emain s a m ajo r c oncern o f producers and users of ic' s. an increase in q ja is the major tradeoff one must accept for package miniaturization. when the user considers all of the variables that af fect the ic junction temperature, he is then prepared to take maximum advantage of the tools, materials and data that are available. references 1. ahigh performance ecl data eclinps and eclinps lite,o motorola, pp. 432. 2. athermal considerations for advanced logic families; an241,o philips semiconductors
15 motorola reliability audit program summary the motorola logic reliability audit program (rap) is designed to monitor the ability of logic products to exceed minimum acceptable reliability standards. mesa reliability engineering has overall responsibility for rap , including updating r equirements , i nterpretin g r esults , o ffshore administration, and monthly reporting. testing rap is a system of mechanical, environmental, and electrical tests performed periodically on randomly selected samples o f s tandar d p roducts. e ac h s ampl e r eceives minimum s tandar d t est s c overin g a l l w afe r f a b s ites, assembly sites, and packages. within each family , devices are chosen to represent the range of die sizes and functional complexity. in addition to standard tests, each package type also receives special preconditioning tests, the frequency of which is intended to sample every package type and assembly site once per month. reliability tests are run at three sites: mesa, arizona (licd); m anila , p hilippine s ( mpi) ; a n d t aipei , t aiwan (metl). following mechanical and electrical testing, devices receive standard static and functional electrical tests using conditions and limits per applicable device specifications. failures all failed devices require recorded data. failure data and failure verification information accompany all rejects to a product analysis lab where root cause failure analysis is performed on all occurrences observed at that site. all information regarding failed units is logged into a tracking database. a review is called if any sample has a failure. the findings are analyzed relative to past performance to determine if customers are at risk for abnormally high failure rates. customer notification may then be required and, if needed, is prepared and distributed. following the completion of testing and data review , the local reliability engineering group enters all data into the reliability audit program database. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer .
16 motorola literature distribution centers: usa: motorola literature distribution; p .o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature centre; 88 t anners drive, blakelands, milton keynes, mk14 5bp , england. jap an: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, t okyo 141 japan. asia-p acific: motorola semiconductors h.k. ltd.; silicon harbour center , no. 2 dai king street, t ai po industrial estate, tai po, n.t., hong kong. br1458s/d
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